Two-transistor type non-volatile semiconductor memory

Details Two-transistor type non-volatile semiconductor memory Two-transistor type non-volatile semiconductor memory

1990-07-27

1992-02-18

Wojciechowicz, Edward J.

357 237, 357 2311, 357 41, 357 49, 357 52, 357 55, H01L 2978

Patent

active

050898663

ABSTRACT:
A non-volatile semiconductor memory comprises a P-type semiconductor substrate having an active region defined by a field isolation region, and a non-volatile memory cell composed of a floating gate N-channel transistor for programming and a floating gate P-channel transistor for reading. The floating gate N-channel transistor is formed in the active region of the substrate. The flaoting gate P-channel transistor includes a source region and a drain region both formed in a conductive semiconductor layer located in the field isolation region, a floating gate formed through an insulating layer above a portion of the conductive semiconductor layer between the source region and the drain region, and a control gate formed through an insulating layer above the floating gate. The floating gate of the P-channel transistor is formed of an extension of a floating gate of the N-channel transistor, and the control gate of the P-channel transistor is connected commonly to a control gate of the N-channel transistor.

REFERENCES:
patent: 4778775 (1988-10-01), Tzeng
J. Pathak et al., "A 50 MHz CMOS Programmable Logic Device", ISSCC '88, THAM 11.4, pp. 144-145.

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