Electronic clock with capacitative resetting

Details Electronic clock with capacitative resetting Electronic clock with capacitative resetting

1976-04-23

1977-05-17

Weldon, Ulysses

Electricity: circuit makers and breakers

Multiple circuit control

Pivoted contact

200DIG1, 58 855, G04C 300

Patent

active

040233430

ABSTRACT:
A reset system for a digital electronic clock of the multistage counter type. Means are provided for deriving from the mains alternating current timing pulses at a frequency substantially higher than 1 Hz and a frequency divider chain derives from these timing pulses, resetting pulses at a frequency higher than 1 Hz and stepping on pulses for the seconds counter at a frequency of 1 Hz. The timing pulses are converted into gating signals by capacitative keys and resettable monostable circuits. The resetting pulses are applied to the counters through AND-gates controlled by the resettable monostable circuits and through OR-gates, the latter receiving also the pulses for stepping on the counters.

REFERENCES:
patent: 3541779 (1970-11-01), Langley
patent: 3742699 (1973-07-01), Bergey
patent: 3762152 (1973-10-01), Marz
patent: 3940920 (1976-03-01), Nakamura et al.
patent: 3983690 (1976-10-01), McClintock

Affiliated with

Also associated with

Rating

Electronic clock with capacitative resetting does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic clock with capacitative resetting, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic clock with capacitative resetting will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1827055