Method and arrangement for use in the elimination of echoes in a

Multiplex communications – Wide area network – Packet switching

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379410, H04B 320

Patent

active

054467284

ABSTRACT:
The invention relates to echo elimination in a subscriber line circuit having digital signal processing. Echo elimination is effected with the aid of a digital balance filter which is connected in an interface where the sampling frequency, e.g. 16 kHz, is higher than the original sampling frequency, e.g. 8 kHz, of transmitted signals. The requisite size of the balance filter can be reduced by sampling the filter at the same frequency, e.g. 8 of kHz, as the original sampling frequency of the transmitted signals.

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patent: 5155743 (1992-10-01), Jacobs
Eriksson and Svensson, "Line Circuit Component SLAC for AXE 10," Ericsson Review No. 4, 1983, pp. 186-191.
P. Defraeye et al., "A 3-.mu.M CMOS Digital Codec With Programmable Echo Cancellation and Gain Setting," IEEE Journal of Solid State Circuits, SC-20, No. 3, Jun. 1985, pp. 676-687.

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