Self-checking arithmetic unit

Details Self-checking arithmetic unit Self-checking arithmetic unit

1979-12-31

1982-02-02

Malzahn, David H.

Boots, shoes, and leggings

G06F 1114

Patent

active

043143504

ABSTRACT:
A circuit for the detection of errors in single and double word arithmetic logic unit operations.
A microprogram processor achieves self-checking of arithmetic logic unit functions by performing single-word operations in the duplex mode and double-word operations in the simplex mode. The double-word operation is checked by performing the operation twice, generating a parity bit for each output word and comparing the parity bits generated for the two operations.

REFERENCES:
patent: 2861744 (1958-11-01), Schmitt et al.
patent: 3660646 (1972-05-01), Minero et al.
patent: 3829668 (1974-08-01), Naumi et al.
patent: 3846626 (1974-11-01), Yoshida

Affiliated with

Also associated with

Rating

Self-checking arithmetic unit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-checking arithmetic unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-checking arithmetic unit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1824722