Developing method and apparatus of hierarchical graphic data for

Details Developing method and apparatus of hierarchical graphic data for Developing method and apparatus of hierarchical graphic data for

1994-01-31

1995-08-29

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

054466750

ABSTRACT:
A system and apparatus for using hierarchically organized data to design semiconductor integrated circuits is herein disclosed wherein a plurality of macros and circuit logic cells containing circuit component parameter information are cross referenced using two types of pointers. An intermediate table 27 in a logic development file 5 stores information relating to a general controlling macro "CHIP", user defined macros A, B, and also stores the parameter information relating to every macro. A cell table 28 stores circuit cells C, D, E, F. The macro "CHIP" A, B, and cells, and the macro and cell are cross referenced by multi-table and an identical table pointer.

REFERENCES:
patent: 5231590 (1993-07-01), Kumar et al.
patent: 5301318 (1994-04-01), Mittal
patent: 5384710 (1995-01-01), Lam et al.
patent: 5396435 (1995-03-01), Ginetti

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