Voltage clamping circuit

Details Voltage clamping circuit Voltage clamping circuit

1979-10-11

1982-02-02

Mullins, James B.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, H03K 508

Patent

active

043141676

ABSTRACT:
A voltage clamping circuit for use in coupling line voltage signals to logic control circuitry used in domestic appliances includes a voltage dropping resistor coupled between input and output terminals. A first enhancement mode MOS transistor is coupled between a junction of the resistor and the output terminal and the V.sub.DD line. The gate of the first transistor is connected to the junction, so that when the voltage at the junction rises to a threshold voltage above V.sub.DD the first transistor is rendered conductive and clamps the positive line voltage cycle. A second enhancement mode MOS transistor is connected between the junction and the V.sub.DD line and its gate is connected to a biasing means which holds the second transistor nonconductive in response to the line voltage going negative until the junction is just above the V.sub.SS level, whereafter the second transistor turns on and clamps the input above V.sub.SS.

REFERENCES:
patent: 3809926 (1974-05-01), Young

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