Communications: electrical – Digital comparator systems
Patent
1994-03-16
1995-08-29
Heyman, John S.
Communications: electrical
Digital comparator systems
395900, G06F 702
Patent
active
054464382
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a logic circuit in which an output word can be formed from first and second input words using bit comparators and bit multiplexers.
A digital logic circuit of this type is disclosed in the publication entitled "A VLSI Fuzzy Logic Controller With Reconfigurable, Cascadable Architecture" by H. Watanabe et al from IEEE Journal of Solid-State Circuits, Volume 25, No. 2, April 1990 (pages 376 to 382). This concerns relatively detailed information on the design of a fuzzy logic controller, information being contained, inter alia, on circuitry for implementing fuzzy logic operators (minimum and maximum). The digital logic circuits (minimum and maximum functions) are relatively simply designed and have a multi-stage serial structure which, starting with the LSBs (least significant bits) of the input words and ending with the MSBs (most significant bits) of the input words do not enable valid bits of an output word until the MSB of the output word is present.
The Proceedings of the Twentieth International Symposium on Multiple-valued Logic, 23.-25. May 1990, Charlotte, N.C., USA, pages 122 to 125 discloses a maximum circuit of a quick fuzzy logic processing unit which comprises cascaded blocks having bit comparators and bit multiplexers, it being possible, starting with the MSB of the input words to carry a less-than carry signal and an equal-to carry signal from stage to stage as far as the LSB.
EDN Electrical Design News, Volume 34, No. 13, 22 June 1989, pages 232 to 234, VANDIVER: "Register performs binary search" discloses a comparator which comprises comparator blocks which are connected via lines for a less-than carry signal, an equal-to carry signal and a greater-than carry signal, the inputs for the carry signals for the block which contains the LSB being permanently prescribed, and it being possible for the carry signals to be carried from stage to stage as far as the block with the MSB.
Summary of the Invention
The object of the invention is to specify a digital logic circuit in which processing starts with the combination of the MSBs of the two input words and further bits of the output word can be generated with falling significance sequentially in time, and in which the design can be as simple as possible.
The object is achieved according to the invention by a digital logic circuit, in which an output word can be formed from a first input word and a second input word using bit comparators and bit multiplexers. The output word is present at an output of the logic circuit and at outputs of the bit multiplexers. The output word represents a minimum of two input words, in which a stage is provided for each bit of the output word. Each i-th stage forms from an i-th bit of the first input word, an i-th bit of the second input word, a less-than input signal of a next more significant (i+1)-th stage, a greater-than input signal of the next more significant (i+1)-th stage and an equal-to input signal of the next more significant (i+1)-th stage a less-than output signal for a next less significant (i-1)-th stage, a greater-than output signal for the next less significant (i-1)-th stage, an equal-to output signal for the next less significant (i-1)-th stage and an i-th bit of the output word. For the most significant stage an input for the less-than input signal and an input for the greater-than input signal are supplied with a logic zero and an input for the equal-to input signal is provided with a logic one. The bits of the output word can be generated sequentially in time at the output of the logic circuit with decreasing significance.
In a modification of the present invention the most significant stage and/or a least significant stage are designed such that it is possible in the most significant stage to form only from a most significant bit of the first input word and a most significant bit of the second input word a less-than output signal, a greater-than output signal and an equal-to output signal for a next less significant stage and a most signifi
REFERENCES:
patent: 4414676 (1983-11-01), Kraul et al.
patent: 4760374 (1988-07-01), Moller
patent: 4857882 (1989-08-01), Wagner et al.
"Quelques applications des Additionneurs T.T.L." Electronique Industrielle No. 124, Jun. 1969 pp. 415-422 by Krausener.
"Comparison Look-Ahead and Design of Fast Fuzzy Operation Units", Han et al., Proceedings 20th Int. Symposium on Multiple-Valued Logic, (1990) pp. 121-125.
"Register performs binary search", Vandiver, EDN Electrical Design News, vol. 34, No. 13, Jun. 22, 1989, pp. 232-234.
"A VLSI Fuzzy Logic Controller with Reconfigurable, Cascadable Architecture", H. Watanabe et al., IEEE Journal of Solid-State Circuits, vol. 25, No. 2, Apr. 1990, pp. 376-382.
Heyman John S.
Siemens Aktiengesellschaft
LandOfFree
Digital logic circuit for implementing fuzzy logic operators does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital logic circuit for implementing fuzzy logic operators, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital logic circuit for implementing fuzzy logic operators will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1822627