Multiprocessor level change synchronization apparatus

Details Multiprocessor level change synchronization apparatus Multiprocessor level change synchronization apparatus

1986-06-27

1989-01-31

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1314

Patent

active

048020877

ABSTRACT:
An apparatus is included within the bus interface circuits of each processing unit of a multiprocessing system which connect in common with the other units of the system to an asynchronous system bus. The apparatus and interrupt signal couple to the processing unit's level register and interrupt circuits. In response to a command specifying a level change, the apparatus conditions these circuits to store level and interrupt signals applied to the system bus as part of such CPU command during a bus cycle of operation granted to the processing unit on a priority basis. This ensures the reliable switching between interrupt levels and the notification of such level changes to the other units of the system without interference from other processing units.

REFERENCES:
patent: 4035780 (1977-07-01), Kristick et al.
patent: 4459665 (1984-07-01), Miu et al.
patent: 4464717 (1984-08-01), Keeley et al.
patent: 4470111 (1984-09-01), Jenkins et al.

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