Method for manufacturing a trench in a substrate for use in smar

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 62, 437228, H01L 2176

Patent

active

054459885

ABSTRACT:
A method for manufacturing a trench in a substrate that has at least a first silicon layer, an insulating layer and a second silicon layer is disclosed. A first trench etching through the first silicon layer down to the insulating layer is implemented using a trench mask. By reinforcing the trench mask with a non-conformally deposited protective layer, the insulating layer is etched through down to the second silicon layer in a second trench etching. The method is particularly suited for the manufacture of insulation trenches having integrated substrate contacting for smart-power technology on an SOI substrate.

REFERENCES:
patent: 4493740 (1985-01-01), Komeda
patent: 4666556 (1987-05-01), Fulton et al.
patent: 4666557 (1987-05-01), Collins
patent: 4872947 (1989-10-01), Wang et al.
patent: 4900692 (1990-02-01), Robinson
patent: 5008210 (1991-04-01), Chiang et al.
patent: 5017999 (1991-05-01), Roisen
patent: 5036021 (1991-07-01), Goto
patent: 5043292 (1991-07-01), Aronowitz et al.
patent: 5049521 (1991-09-01), Belanger et al.
patent: 5077228 (1991-12-01), Eklund et al.
patent: 5096848 (1992-03-01), Kawamura
patent: 5116779 (1992-05-01), Iguchi
patent: 5120675 (1992-06-01), Pollack
S. Wolf, Silicon Processing for VLSI Era. vol. 2, pp. 204-206, copyright 1990 by Lattice Press.
IBM "Technical Disclosure Bulletin", vol. 34, No. 9, Feb. 1992, entitled Soft Error Rate Reduction in Trench Technology, p. 117.
A. Nakagawa et al., "New 500V Output Device Structures for Thin Silicon Layer on Silicon Dioxide Film", International Symposium on Power Semiconductor Devices & IC's, (1990), pp. 97-101.
Y. Ohata et al., "Dielectrically Isolated Intelligent Power Switch", IEEE 1987 Custom Integrated Circuits Conference, pp. 443-446.
K. D. Beyer et al., "Borosilicate Glass Trench Fill", IBM Technical Disclosure Bulletin, vol. 27, No. 2 Jul. 1984, pp. 1245-1247.
"Formation of Thermal Isolation Cap Oxide", IBM Technical Disclosure Bulletin, vol. 33, No. 4 Sep. 1990, pp. 463-465.
K. Shenai, "A Novel Trench Planarization Technique Using Polysilicon Refill, Polysilicon Oxidation, and Oxide Etchback", IEEE Transactions on Electron Devices, vol. 40, No. 2, Feb. 1993, pp. 459-463.
Patent Abstract of Japan, T. Ezaki, "Forming Method for Isolating Region", 62-257575, Apr. 18, 1989, E-795, Jul. 28, 1989, vol. 13/No. 338, pp. 149-151.
J. Wang, "Selective Substrate Contact With Dual Width Trenches", Motorola Inc., Technical Developments, vol. 18, Mar. 1993, pp. 18-21.
IBM Technical Disclosure Bulletin, "Trench Filling Process"; vol. 28, No. 6, Nov. 1985, pp. 2583-2584.
IBM Technical Disclosure Bulletin, "Fabrication of a Sub-Minimum Lithography Trench", vol. 29, No. 6, Nov. 1986, pp. 2760-2761.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for manufacturing a trench in a substrate for use in smar does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing a trench in a substrate for use in smar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a trench in a substrate for use in smar will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1819278

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.