Method and apparatus for incrementing a digital word

Details Method and apparatus for incrementing a digital word Method and apparatus for incrementing a digital word

1981-07-14

1983-11-22

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

044173156

ABSTRACT:
A circuit is presented designed specifically for use in complementary symmetry design techniques such as CMOS/SOS wherein inverting gate types are a preferred design. This design is obtained with a minimum of delay by changing gate types in the ripple carry path wherein alternating stages utilize NAND gates with the remaining ripple carry path stages using NOR gates. To accomplish this approach, the bit stages of the word utilizing the NOR gates must have the bits inverted before being applied to the incrementing circuit.

REFERENCES:
patent: 3989940 (1976-11-01), Kihara
patent: 4052604 (1977-10-01), Maitland et al.
patent: 4054788 (1977-10-01), Maitland et al.
patent: 4153939 (1979-05-01), Kudov
patent: 4218750 (1980-08-01), Carter et al.
patent: 4280190 (1981-07-01), Smith
Elliott, "Increment-Decrement Logic", IBM Tech. Disclosure Bulletin, vol. 11, No. 3, Aug. 1968, pp. 297-298.

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