Programmable multiple CCD clock synthesizer

Details Programmable multiple CCD clock synthesizer Programmable multiple CCD clock synthesizer

1996-12-30

1998-12-08

Le, Dinh

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327141, 327172, 327258, 327105, 377 77, 377 78, H03K 1700, H03K 513

Patent

active

058475885

ABSTRACT:
The clock synthesizer includes an oscillator section for providing a train of pulses corresponding to the transitions of a master clock signal, a first register coupled to the oscillator for dividing the train of pulses by a fixed integer to produce a plurality of first phase shifted signals corresponding in number to said integer, and a plurality of second shift registers corresponding in number to the integer and each having a clocking input coupled to a respective one of the first phase shifted signals. The second registers produce a plurality of second phase shifted signals having leading edge transitions separated from each other by displacements corresponding to the transitions of the master clock signal. The second phase shifted signals are then combined to generate the lower frequency clock pulses, which may be used, e.g., in the clocking of a charge coupled device image sensor.

REFERENCES:
patent: 4700350 (1987-10-01), Douglas et al.
patent: 5039950 (1991-08-01), McDermott

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