Boots – shoes – and leggings
Patent
1981-11-13
1983-11-22
Thomas, James D.
Boots, shoes, and leggings
G06F 300
Patent
active
044173040
ABSTRACT:
A cycle steal mechanism for enabling a host processor to initiate and control the cycle stealing of data to or from a storage unit located in an I/O controller which is connected to the I/O channel bus of the host processor. The I/O controller also includes a microprocessor and a direct memory access (DMA) unit either or both of which can be used to control the transfer of data between the I/O controller storage unit and the host processor. Typically, the DMA unit is used for cycle stealing data between the controller storage unit and the host processor. The cycle steal mechanism of the present invention enables the host processor to also initiate and control the cycle stealing of data to or from the controller storage unit without interrupting the program running in the controller microprocessor and without interrupting the cycle stealing operations of the DMA unit. This new cycle steal mechanism is the reverse of the normal situation where it is the microprocessor or DMA unit that is controlling the cycle stealing. Since the I/O controller accommodates both kinds of cycle stealing, the present invention can be said to provide a "2-way" cycle stealing capability. Not only can the I/O controller cycle steal data to or from the host processor main storage unit, but also the host processor can cycle steal data to or from the I/O controller storage unit. The cycle stealing by the host processor is transparent to both the microprocessor and the DMA unit in the I/O controller. This new cycle steal mechanism makes use of the microprocessor address set-up pulse (ALE) and the DMA unit address set-up pulse (ADSTB) to cause the cycle stealing of the data to or from the controller storage unit to occur during such address set-up time. These address set-up times are times when neither the microprocessor nor the DMA unit is actually moving data into or out of the storage unit in the I/O controller.
REFERENCES:
patent: 3961312 (1976-06-01), Bodner et al.
patent: 3972023 (1976-07-01), Bonner et al.
patent: 3996564 (1976-12-01), Kerrigan et al.
patent: 4038642 (1977-07-01), Bouknecht et al.
patent: 4096578 (1978-06-01), Malkemes
patent: 4128876 (1978-12-01), Ames et al.
patent: 4131944 (1978-12-01), Mager et al.
patent: 4181934 (1980-01-01), Marenin
Rothlisberger, H.: a paper entitled "A Standard Bus for Multiprocessor Architecture" appearing in a book entitled Microcomputer Architectures, North-Holland Publishing Company, 1977.
Adams, G. et al.: "Design Motivations for Multiple Processor Microcomputer Systems, Computer Design", Mar. 1978.
Associated Computer Consultants, "Unibus Micro-Channel UMC-Z80 Processor Board", Apr. 1978.
Kinnie et al., "Dual-Port RAM Hikes Throughput in I/O Controller Board", Electronics, pp. 107-112, 8/17/78.
Samuelson, "Intelligent Controller Increases Data Throughput, Reduces Host Overhead", Computer Design, pp. 120-126, Jul. 1979.
Motorola Semiconductor Products Inc., "MC6881/MC3449 Triple Bi-Directional Bus Switch".
Bee Richard E.
Eng David Y.
International Business Machines - Corporation
Thomas James D.
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