Low power noise rejecting TTL to CMOS input buffer

Details Low power noise rejecting TTL to CMOS input buffer Low power noise rejecting TTL to CMOS input buffer

1992-02-13

1993-06-01

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 3072722, H03K 1716, H03K 19094

Patent

active

052162990

ABSTRACT:
A lower power, noise rejecting TTL-to-CMOS input buffer, without the use of a current consuming voltage reference, has the characteristic of recognizing a logic LOW as less than 0.8 volts and a logic HIGH as greater than 2.0 volts for DC TTL signals while drawing only leakage current from its Vcc power supply, and simultaneously possesses the characteristic of rejecting high-amplitude Vin noise. For an input signal rapidly rising from zero to three volts, the buffer output switches at an input signal level of approximately 2.5 volts; and for the input signal rapidly falling from 3 to zero volts, the buffer output switches at an input signal level of approximately 1.4 volts.

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patent: 4486670 (1984-12-01), Chan et al.
patent: 4532436 (1985-07-01), Bismarck
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patent: 4845381 (1989-07-01), Cuevas
patent: 4978870 (1990-12-01), Chen et al.
patent: 4980583 (1990-12-01), Dietz
patent: 5159206 (1992-10-01), Tsay et al.

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