Single chip microprocessor circuits, systems, and methods for se

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Details

395385, G06F 9445, G06F 930

Patent

active

059500123

ABSTRACT:
In a method embodiment (34), the method operates a computer system (10) having a type of configuration and including a single integrated circuit microprocessor (24). The microprocessor operates in response to codes and has an instruction set. The method involves various steps, including determining (40) the type of the configuration. In response to the type of the configuration, the method selects (42) a set of patch codes from a plurality of sets of patch codes. The method also issues (54) a patch request instruction from the instruction set, and it stores (56) the selected set of patch codes to a memory space accessible by the microprocessor. Other circuits, systems, and methods are also disclosed and claimed

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On-Site ROS Patch Mechanism, IBM Technical Disclosure Bulletin, vol. 30, No. 5, pp. 158-160, Oct. 1987.
Method of Customizing Patches for Each Hardware Configuration, IBM Technical Disclosure Bulletin, vol. 27, No. 4A, pp. 2187-2188, Sep. 1984.

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