Patent
1997-07-03
1999-09-07
An, Meng-Ai T.
395308, 395287, G06F 1300
Patent
active
059499818
ABSTRACT:
A mechanism is provided for avoiding deadlock, in particular, a Read/Read deadlock, in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, deadlock is avoided using a closely-coupled master and slave circuit on the split-response bus. The closely-coupled master and slave circuit operates to disallow a second deadlocking read transaction. While there is an outstanding read transaction in either the master or slave portions of the split-response bus interface, the other portion will refuse to accept, or retry, another potentially deadlocking read transaction. The invention has the advantage of being absolutely certain of avoiding the Read/Read deadlock condition with a minimum amount of circuit complexity.
REFERENCES:
patent: 4494193 (1985-01-01), Brahm et al.
patent: 5278974 (1994-01-01), Lemmon et al.
patent: 5305442 (1994-04-01), Pedersen et al.
patent: 5345562 (1994-09-01), Chen
patent: 5355455 (1994-10-01), Hilgendorf et al.
patent: 5363485 (1994-11-01), Nguyen et al.
patent: 5418914 (1995-05-01), Heil et al.
patent: 5469435 (1995-11-01), Krein et al.
patent: 5546546 (1996-08-01), Bell et al.
An Meng-Ai T.
Apple Computer Inc.
Lefkowitz Sumati
LandOfFree
Deadlock avoidance in a bridge between a split transaction bus a does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Deadlock avoidance in a bridge between a split transaction bus a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Deadlock avoidance in a bridge between a split transaction bus a will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1813355