Digitally controlled phase locked loop system

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358140, 358159, 375120, 331 25, H04N 506

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active

048020095

ABSTRACT:
A phase locked loop system for generating a line-locked clock signal for a television signal processing system includes an analog phase-locked loop nested within a digital phase locked loop. The analog phase-locked loop is synchronized to a reference signal which is derived from the most significant bit of a digital oscillator signal generated by a clocked digital oscillator. To reduce instability in this reference signal, the ratio of the frequency of the clock signal to the frequency of the digital oscillatory signal is chosen to be a noninteger value greater than two. In one embodiment of the invention the stability of the reference signal is further enhanced by adaptively delaying transitions in the reference signal by amounts of time that are inversely proportional to the value of the less significant bits of the samples corresponding to the transitions.

REFERENCES:
patent: 4349833 (1982-09-01), Clarke
patent: 4476490 (1984-10-01), Kaneko
patent: 4488170 (1984-12-01), Nillesen
patent: 4489342 (1984-12-01), Gollinger et al.
patent: 4500909 (1985-02-01), Machida
patent: 4520319 (1985-05-01), Baker
patent: 4600895 (1986-07-01), Landsman
patent: 4639780 (1987-01-01), Willis
patent: 4652832 (1987-03-01), Jasper
patent: 4679005 (1987-07-01), Tatami
patent: 4689582 (1987-08-01), Balaban
Nillesen, A. H. H. J., "Line-Locked Digital Colour Decoding" Electronic Components and Applications, vol. 7, No. 4, 1986, pp. 239-245.
Gruen, W. I., "Theory of AFC Synchronization Proceedings of the IRE", Aug., 1953, pp. 1043-1048.

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