Sequence controller of an instruction processing unit for placin

Details Sequence controller of an instruction processing unit for placin Sequence controller of an instruction processing unit for placin

1990-08-14

1992-06-09

Clark, David L.

G06F 900

Patent

active

051214881

ABSTRACT:
A sequence controller of an instruction processing unit (IPU) in a data processing system places the IPU is either a ready, go, hold-on-old, hold-on-new, or cancel state. If the IPU is ready to execute another instruction, the sequence controller places the IPU in the ready state. When an instruction is received for execution, and execution commences, the sequence controller places the IPU in the GO state. If at least one or more operands associated with the execution of an instruction are not ready when execution is scheduled to commence, the sequence controller places the IPU in a hold-on-new state, holding the pendency of the execution of the particular instruction, until the operands are available. If one or more other functional units in the data processing system are not ready (busy) during execution of the instruction, and the other functional units are needed to complete execution of the instruction, the sequence controller places the IPU in a hold-on-old state, holding the execution results thus far generated, until the functional units become availabale. If the functional unit remains busy, or if an error in the functional unit is confirmed, the sequence controller places the IPU in the cancel state. If the functional unit recovers from the error, and/or the functional unit is no longer busy, the sequence controller causes the IPU to leave the hold-on-old state, and the execution of the instruction is completed. When the one operand becomes available, the sequence controller causes the IPU to leave the hold-on-new state, and the execution of the instruction is completed.

REFERENCES:
patent: 3943494 (1976-03-01), Holmes, Jr. et al.
patent: 4155120 (1979-05-01), Keefer et al.
patent: 4384324 (1983-05-01), Kim et al.
patent: 4532589 (1985-07-01), Shintani et al.
patent: 4574348 (1986-03-01), Scallon
patent: 4590554 (1986-05-01), Glazer et al.
patent: 4594655 (1986-06-01), Hao et al.
Sriui V. P., "A Fault Tolerant Dataflow System," IEEE Computer, Mar. 1985, pp. 54-68.
European Search Report dated Jan. 17, 1991, EPO Form 1507 07.90 Communication.
Architectural Advances Spur 32-Bit Micros, by John Bond, Computer Design, Jun. 1, 1984, pp. 125-136.
The Architecture of Pipelined Computers, by Peter M. Kogge, 1981, pp. 225-246.

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