Method of organizing programmable logic array devices for board

Details Method of organizing programmable logic array devices for board Method of organizing programmable logic array devices for board

1989-12-20

1992-06-09

Smith, Jerry

Excavating

371 222, H04B 1700

Patent

active

051213940

ABSTRACT:
A system provides for the testing of components which connect to one or more of programmable logic devices (PLDs), each of which is organized in a predetermined manner. Each PLD includes a plurality of programmable logic sections, each of which connect to I/O pins through driver and receiver circuits. An available section includes programmed means for causing its driver circuit to force the I/O pin to a first logic level when made operational. The other sections each include programmed means for connecting their associated driver circuits to be controlled by signals applied to the receiver circuit of the available section. During testing, means are externally applied to the I/O pin of the available section which drive the pin from the first logic level to a second logic level. This causes the receiver circuit to apply signals which inhibit the driver circuits of the remaining sections from applying signals to their I/O pins thereby enabling the testing of components which connect to these I/O pins without interference.

REFERENCES:
patent: 4488301 (1984-12-01), Nasuta et al.
patent: 4546472 (1985-10-01), Volk et al.
patent: 4571724 (1986-02-01), Belmondo et al.
patent: 4973904 (1990-11-01), Sonnek
Mastrocola, Effective Utilization of IN-Circuit Techniques When Testing Complex Digital Assemblies, Aug. 1981.

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