Multi-processor computer system with interrupt controllers provi

Details Multi-processor computer system with interrupt controllers provi Multi-processor computer system with interrupt controllers provi

1996-09-17

1997-12-23

Ray, Gopal C.

395733, 395737, 395868, G06F 1326

Patent

active

057014965

ABSTRACT:
A multi-processor programmable interrupt controller system that includes: an I/O interrupt controller for receiving interrupt requests from an I/O subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for bus and priority arbitration, using a standard message format and arbitration protocol. The system is implemented, in part, by incorporating the processor interrupt controller with its associated processor into a single integrated circuit. The common system bus which normally carries all system traffic is not used for interrupt request messages. The interrupt controller bus is used for this purpose and thus results in a more efficient system by relieving the system bus of interrupt service requests and the related interrupt request traffic.

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