Data processor

Patent

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Details

395590, 395584, 395800, G06F 938, G06F 940, G06F 942

Patent

active

057014493

ABSTRACT:
A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

REFERENCES:
patent: 4315313 (1982-02-01), Armstrong et al.
patent: 4394729 (1983-07-01), Armstrong
patent: 4399507 (1983-08-01), Cosgrove et al.
patent: 4546431 (1985-10-01), Horvath
patent: 4974158 (1990-11-01), Watanabe et al.
patent: 5526498 (1996-06-01), Matsuo et al.
Lee, et al., "Branch Prediction Strategies and Branch Target Buffer Design," Computer, (Jan.,1984), pp.6-9.

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