1996-05-30
1997-12-23
Donaghue, Larry D.
395590, 395584, 395800, G06F 938, G06F 940, G06F 942
Patent
active
057014493
ABSTRACT:
A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.
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patent: 5526498 (1996-06-01), Matsuo et al.
Lee, et al., "Branch Prediction Strategies and Branch Target Buffer Design," Computer, (Jan.,1984), pp.6-9.
Matsuo Masahito
Yoshida Toyohiko
Albert Philip H.
Donaghue Larry D.
Mitsubishi Denki & Kabushiki Kaisha
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