Pipelined system for decomposing instruction into two decoding p

Details Pipelined system for decomposing instruction into two decoding p Pipelined system for decomposing instruction into two decoding p

1992-11-09

1994-11-01

Lall, Parshotam S.

Boots, shoes, and leggings

3642318, 3642475, 3642476, 3642599, G06F 930, G06F 934

Patent

active

053613384

ABSTRACT:
A pipelined data processor decomposes an instruction into a plurality of processing units (step codes), each corresponding to an operand of the instruction. In the register direct addressing mode, where the source operand of the instruction is an immediate value and the destination operand of the instruction is a register, the data processor combines the two step codes associated with the two operands into one. Thus, the number of cycles required for processing the instruction is reduced.

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