Scheme for error handling in a computer system

Details Scheme for error handling in a computer system Scheme for error handling in a computer system

1992-04-24

1994-11-01

Beausoliel, Jr., Robert W.

Excavating

371 13, H03M 1300

Patent

active

053612671

ABSTRACT:
The present invention is directed to a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor. The control flow logic includes an error checker to check data received from the bus for hard errors and parity errors and an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error. An error signal generator is utilized to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data and a data mover transmits the received data and the ECC to the processor.

REFERENCES:
patent: 4503535 (1985-03-01), Budde et al.
patent: 4837767 (1989-06-01), Hartwell et al.
patent: 4852095 (1989-07-01), Meltzer
patent: 5099485 (1992-03-01), Bruckert et al.
patent: 5263032 (1993-11-01), Porter et al.

Affiliated with

Also associated with

Rating

Scheme for error handling in a computer system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scheme for error handling in a computer system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scheme for error handling in a computer system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1806914