Tunable timer for memory arrays

Details Tunable timer for memory arrays Tunable timer for memory arrays

1991-01-31

1992-06-09

Pascal, Robert J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307289, 307594, 307597, H03K 300

Patent

active

051209870

ABSTRACT:
The present invention is directed to a tunable delay element incorporating one-half of a bipolar SRAM cell and a reference generator. In operation, the rising edge and incoming clock pulse sets the receiver/latch, latching the internal clock (i.e., the write pulse). The same rising edge of the clock pulse also functions to initiate the switching of the half memory cell in the tunable delay. When the half memory cell is switched halfway to its second state (relative to the referenced generator) the latch is disabled and the ICL write pulse goes low. The ICL write pulse is thus self-timed to be operational in the actual memory cell. Some delay circuitry is also provided for controlling the switching speed of the half memory cell in the tunable delay in order to selectively adjust the ICL pulse width.

REFERENCES:
patent: 3048708 (1962-08-01), Raver
patent: 3073972 (1963-01-01), Jenkins
patent: 3187201 (1965-06-01), Eastman et al.
patent: 3484624 (1969-12-01), Rasiel et al.
patent: 3532993 (1970-10-01), Kennedy
patent: 4015145 (1977-03-01), Stewart
patent: 4277697 (1981-07-01), Hall et al.
patent: 4574204 (1986-03-01), Bonnet

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