Method and device for protecting the execution of linear sequenc

Details Method and device for protecting the execution of linear sequenc Method and device for protecting the execution of linear sequenc

1995-07-19

1997-12-23

Beausoliel, Jr., Robert W.

Excavating

371 491, 3642663, 3649456, G11C 2900

Patent

active

057013152

ABSTRACT:
A method for detecting errors in a linear sequence of commands executed by a processor and stored in a memory at a predetermined start address, comprises the association of each word in the sequence to a bit of the start address. Before storing each sequence word into the memory, the method determines the value of an unused bit of the word so that the value of the associated bit of the start address will be equal to the result of a predetermined function applied to the bits of the word. When reading a sequence word in said memory, the method compares the result of said function applied to the bits of the word read, with the value of the associated bit of the start address, and transmits an error signal if a difference is detected.

REFERENCES:
patent: 3585378 (1971-06-01), Bouricius
patent: 4074229 (1978-02-01), Prey
patent: 4108359 (1978-08-01), Proto
patent: 4692893 (1987-09-01), Casper
patent: 4811347 (1989-03-01), Bolt
patent: 5392302 (1995-02-01), Kemp et al.
IBM Technical Disclosure Bulletin, vol. 21, No. 6, Nov. 1978.

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