Method for automatically determining wiring routes

Details Method for automatically determining wiring routes Method for automatically determining wiring routes

1991-07-09

1994-11-01

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, G06F 1560

Patent

active

053612140

ABSTRACT:
A method for automatically determining wiring routes among terminals comprising separating the terminals to a group of two-terminal units in which the Manhattan length between two terminals in a unit is statistically shortened to the minimum, calculating a specific length L between the two terminals, roughly determining all the wiring routes connecting each two-terminal unit in which the distance between the two terminals is larger than the specific length L, dividing the routing area into a group of small areas, composing a group of medium areas which are respectively formed by combining four small areas in close proximity, roughly and simultaneously determining all wiring routes of the two-terminal units In which the distance between the two terminals is smaller than the specific length L in the medium areas conceivable as the combination of four small areas in close proximity.

REFERENCES:
patent: 4495559 (1985-01-01), Gelatt, Jr. et al.
patent: 5200908 (1993-04-01), Date et al.
patent: 5202840 (1993-04-01), Wong
patent: 5208759 (1993-05-01), Wong
"A Placement Algorithm for Array Processors" by Chyan et al., IEEE 20th Design Automation Conference, 1987, pp. 182-188.
"A Parallel Processing Approach for Logic Module Placement" by Ueda et al., IEEE Trans. on Computer-Aided Design, vol. CAD-2, No. 1, Jan. 1983, pp. 39-47.
"Placement by Simulated Annealing on a Multiprocessor" by Kravitz et al., IEEE Trans. on Computer-Aided Design, vol. CAD-6, No. 4, Jul. 1987, pp. 534-549.

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