Monolithically integrated semiconductor device and process for f

Details Monolithically integrated semiconductor device and process for f Monolithically integrated semiconductor device and process for f

1987-05-19

1989-01-31

Clawson, Jr., Joseph E.

357 234, 357 38, 357 55, 357 86, H01L 2978

Patent

active

048019852

ABSTRACT:
The present invention relates generally to monolithically integrated gate semiconductor devices and more particularly, to improved semiconductor structures in which the parasitic four layer structure has been modified to avoid the possibility that non-preferred turn-on can occur. The length of the emitter region is reduced to thereby reduce the length of the base emitter junction and the magnitude of the IR voltage drop than can occur along that junction. Further, high density shorts are provided along that junction to prevent the parasitic four layer structure from functioning in a non-preferred latched or regenerative conducting mode. In an alternate embodiment, the parasitic four layer structure has been eliminated. Accordingly, insulated gate control of the device is preserved.

REFERENCES:
patent: 4503598 (1985-03-01), Vora et al.

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