Fishing – trapping – and vermin destroying
Patent
1990-06-01
1992-06-09
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 69, H01L 21285
Patent
active
051206757
ABSTRACT:
A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly therefrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semicondcutor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).
REFERENCES:
patent: H204 (1987-02-01), Oh et al.
patent: 4750971 (1988-06-01), Maas et al.
patent: 4868136 (1989-10-01), Ravaglia
patent: 4889583 (1989-12-01), Chen
patent: 4897366 (1990-01-01), Smeltzer
Barndt B. Peter
Chaudhuri Olik
Donaldson Richard L.
Kesterson James C.
Ojan Ourmazd S.
LandOfFree
Method for forming a trench within a semiconductor layer of mate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a trench within a semiconductor layer of mate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a trench within a semiconductor layer of mate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1804307