Method of forming self-aligned top gate channel barrier region i

Details Method of forming self-aligned top gate channel barrier region i Method of forming self-aligned top gate channel barrier region i

1991-02-06

1992-06-09

Quach, T. N.

Fishing, trapping, and vermin destroying

437 29, 437 45, 437154, 437911, 437978, 148DIG13, 148DIG106, H01L 21236, H01L 21266

Patent

active

051206692

ABSTRACT:
An ion-implanted JFET has a channel barrier region at the top gate surface self-aligned to the source and drain, thereby maintaining sufficient separation between the channel barrier and the source and drain for attaining a high source/drain breakdown voltage. After a top gate and an underlying channel layer are ion-implanted through a thin oxide layer, a first photoresist layer is formed and patterned to expose surface portions of the thin oxide layer where source, drain and channel barrier regions are to be formed. Through these apertures in the first photoresist mask, shallow high impurity concentration surface region are ion-implanted. A second photoresist layer is formed on the first photoresist layer, and patterned to completely expose the first and second apertures in the first photoresist layer and to remove material of the second photoresistor layer down to the surface of the the oxide layer, while masking the barrier region. Source and drain regions are then implanted through the second photoresist layer and the exposed first and second apertures of the first mask. The dose and implantation energy is such that the second implant effectively overrides the shallow regions of the first implant. Because the locations at which the source and drain regions in the underlying semiconductor material are formed are defined by the pattern in the first photoresist mask, the source and drain regions are self-aligned with the barrier region.

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