Method of forming interconnection line

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

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438672, 438742, H01L 2100

Patent

active

059487054

ABSTRACT:
A method of forming an interconnection line of a semiconductor device includes the steps of forming an insulating layer on a substrate, forming a contact hole in the insulating layer, forming a first conductive material layer in the contact hole so that a top surface level of the first conductive material layer is the same as or higher than a top surface level of the insulating layer and so that a portion of the first conductive material layer remains on the insulating layer, and forming a second conductive material layer on the first conductive material layer as the portion of the first conductive material layer remaining on the insulating layer is removed.

REFERENCES:
patent: 4884123 (1989-11-01), Dixit et al.
patent: 5422310 (1995-06-01), Ito

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