Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Patent
1995-03-28
1997-12-23
Ledynh, Bot L.
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
257690, 257734, 257735, H01L 2302
Patent
active
057009759
ABSTRACT:
In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.
REFERENCES:
patent: 5165067 (1992-11-01), Wakefield et al.
patent: 5287000 (1994-02-01), Takahashi et al.
patent: 5331201 (1994-07-01), Nishino
patent: 5394008 (1995-02-01), Ito et al.
patent: 5410173 (1995-04-01), Kikushima et al.
patent: 5422233 (1995-06-01), Anjoh et al.
patent: 5428247 (1995-06-01), Sohn et al.
Dang-hsing Yiu Tom
Hikawa Tetsuo
Ni Ful-Long
Sawada Takashi
Takata Akira
Dang-hsing Yiu Tom
Ledynh Bot L.
Mega Chips Corporation
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