Memory system with single command selective sequential accessing

Details Memory system with single command selective sequential accessing Memory system with single command selective sequential accessing

1980-06-26

1985-05-07

Thomas, James D.

Boots, shoes, and leggings

364706, 364708, G06F 932, G06F 1306, G06F 1502

Patent

active

045162182

ABSTRACT:
This addressing system, advantageously for smaller scale data processors with relatively narrow data paths, facilitates transferring pluralities of multibit data words, e.g., storing or fetching the contents of a multidigit register in a calculator. A bidirectional bus couples a controller and a plug-in memory. The controller generates address, data, and command signals. A decoder receives command signals and outputs signals to a program counter (PC) alternatively indicating a normal mode, in which the controller accesses a single specified memory address, or a multiple access mode, in which a predetermined number of sequential addresses are accessed starting at a specified address. In response to selective command decoder output, the PC alternatively may store received addresses, output stored count values to the controller or to a memory array, or increment the count value in synchronism with data transfers to/from multiple memory locations. The decoder, PC, and memory array are contained within the portable memory module's housing, which may be mounted in another housing containing the controller.
In a ROM embodiment, the mounted memory is powered directly from a source in the controller housing. In a RAM embodiment, the module's housing includes a power switching circuit and an internal battery to provide uninterrupted power to the read/write memory cells irrespective of whether the module is mounted or detached.

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