Floating-gate memory array with silicided buried bitlines and wi

Details Floating-gate memory array with silicided buried bitlines and wi Floating-gate memory array with silicided buried bitlines and wi

1991-01-07

1992-06-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 43, 437 41, 437 52, 357 235, H01L 2170, H01C 2700

Patent

active

051205718

ABSTRACT:
A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The four sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.

REFERENCES:
patent: 4258466 (1981-03-01), Kuo et al.
patent: 4493057 (1985-01-01), McElroy
patent: 4545852 (1985-10-01), Barton
patent: 4652897 (1987-03-01), Okuyama et al.
patent: 4697330 (1987-10-01), Paterson et al.
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 4849369 (1989-07-01), Jeuch et al.

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