Method of fabricating a LDDFET with self-aligned silicide

Details Method of fabricating a LDDFET with self-aligned silicide Method of fabricating a LDDFET with self-aligned silicide

1987-07-09

1989-04-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437229, 437233, 437186, 357 233, 156643, H01L 21265

Patent

active

048187151

ABSTRACT:
A method of fabricating a lightly-doped drain field effect transistor (LDDFET) with or without self-aligned silicide (salicide) on a substrate is disclosed. The initial steps include either (1) anisotropic silicon nitride and polysilicon etching steps, an isotropic photoresist erosion step, and a second anisotropic etching of part of the silicon nitride to obtain a ladder-shaped polysilicon gate having a silicon nitride thereon; or (2) an anisotropic polysilicon etch step, an isotropic photoresist erosion step to expose part of the unetched polysilicon, and a second anisotropic polysilicon etch step to remove completely the unmasked polysilicon to obtain the ladder-shaped polysilicon gate. The LDD structure is formed by the implantation of ions to form a heavily-doped source and drain regions and lightly-doped regions under the step of the ladder-shaped polysilicon gate layer. Thereafter, the thin polysilicon step is oxidized completely. After the silicon nitride and silicon dioxide layers are removed, the self-aligned silicide may be applied to form the LDD with salicide.

REFERENCES:
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patent: 4613883 (1986-09-01), Tihanyi
Tihanyi et al., "DIMOS--A Novel IC Technology with Submicron Effective Channel MOSFETS", IEDM, 1977, pp. 399-401.
Ohta et al., "A Quadruply Self-Aligned MOS (QSA MOS), A New Short Channel High Speed High Density MOSFET for VLSI", IEDM, 1979, pp. 581-583.
Huang et al., "A Novel Submicron LDD Transistor with Inverse T-Gate Structure", IEDM, 1986, pp. 742-745.

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