Method of manufacturing a dual field effect transistor

Details Method of manufacturing a dual field effect transistor Method of manufacturing a dual field effect transistor

1993-04-12

1994-11-01

Quach, T. N.

Fishing, trapping, and vermin destroying

437 41, 437 56, 437133, 437912, H01L 21335

Patent

active

053607554

ABSTRACT:
A method of manufacturing a field effect transistor comprises sequentially epitaxially growing on a semi-insulating compound semiconductor substrate an active layer of the first compound semiconductor having a first dopant concentration and a source layer of the first compound semiconductor having a second dopant concentration higher than the first dopant concentration, removing part of the source layer to leave a source region on the substrate, forming a gate electrode on the active layer spaced from the source region, forming a drain region in the substrate spaced from the gate electrode, on the opposite side of the gate electrode from the source region, adjacent to and in contact with the active layer and having a dopant concentration intermediate the dopant concentrations of the active layer and the source region, and forming source and drain electrodes on the source and drain regions, respectively.

REFERENCES:
patent: 5001536 (1991-03-01), Fukuzawa et al.
patent: 5021857 (1991-06-01), Suehiro
patent: 5041393 (1991-08-01), Ahrens et al.
patent: 5112766 (1992-05-01), Fujii et al.
patent: 5196359 (1993-03-01), Shih et al.
patent: 5240869 (1993-08-01), Nakatani
patent: 5270228 (1993-12-01), Ishikawa
Wolf et al., Silicon Processing, vol. 1, Lattice Press, 1986, pp. 565-568.
Matsunaga et al, "Half-Micron Gate GaAs MESFET Technology Using Selectively-Grown N.sup.+ Layer For High Speed Static RAM Fabrication", IEEE GaAs Symposium, 1989, pp. 147-150.
Imamura et al, "A WSi/TiN/Au Gate Self-Aligned GaAs MESFET With Selectively Grown n.sup.+ Layer Using MOCVD", Japanese Journal of Applied Physics, vol. 23, No. 5, 1984, pp. L342-L345.

Affiliated with

Also associated with

Rating

Method of manufacturing a dual field effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a dual field effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a dual field effect transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1802217