Patent
1993-07-02
1996-07-16
Beausoliel, Jr., Robert W.
395405, G06F 1134
Patent
active
055376215
DESCRIPTION:
BRIEF SUMMARY
The invention relates to a method for managing an integrated electronic memory that may include defects, the resultant memory, and the system employing this method. More particularly, the invention applies to information processing systems and to the cache memories of such systems.
An information processing system is made up of a central subsystem that can communicate with one or more peripheral subsystems by way of input/output units. The central subsystem of a large system ordinarily includes several processors connected by a bus to a central memory and the input/output units.
The function of each processor is to execute the instructions of the programs contained in the central memory. These instructions and the data necessary for executing them are accessible by the processor by using the addressing means of the central memory. However, given the relatively long access time in the central memory, the processors are typically provided with a cache memory that is much faster but with contents limited to a certain number of extracts from the contents of the central memory. A cache memory is composed of a data memory and a directory of addresses of the memory data. The data memory is generally embodied by a static random access memory (SRAM) and constitutes a multilevel associative memory with levels. It is divided into blocks each of the same predetermined size and each corresponding to one quantum of exchange with the central memory. The blocks are organized into N columns of n levels. N consecutive blocks constitute one page of the cache memory, which accordingly contains a total of n pages. The address of a block in a page accordingly corresponds to a column. However, a block at a given address may be placed in any level of the column. The level of a block is determined by performing a comparison with the addresses of the pages of the column. In order to shorten the duration for searching a block, a small number of levels, ordinarily two or four, is assigned to each column.
A processor is made up of various processing circuits. A description of these circuits adapted to a microprogrammed processor may be found in European Patent Application A-0434483, corresponding to U.S. Ser. No. 07/620,130 of DOLIDON et al., filed Nov. 30, 1990, for "Process With Multiple Microprogrammed Processing Units", filed by the assignee of the present application for example. In this reference, the processors were connected by way of their cache memory to a bus, enabling them to communicate with the memory. Each processor and its cache memory resided together on the same printed wiring board connecting a plurality of integrated circuit packages.
Because the capacity to integrate circuits is ceaselessly increasing, it is now possible to integrate each processor in a chip and to associate a cache memory portion, called private cache memory, with it. The private cache memories are connected to an external cache memory part, known as shared cache memory and connected to the bus. A private cache memory is also composed of a data memory and an address memory.
The invention relates to the problem presented by defects, faults or errors in the components and/or circuits of the memory. To overcome them, it is known to add reserve components in circuits and to reconfigure the circuits of the memory. The reconfiguration consists in disconnecting the defective part and replacing it by using the reserve circuits and components. In another solution, redundant functional parts such as memory blocks are added and used in place of the corresponding defective parts. A decoder is added to the directory of the memory for the allocation of the redundant parts.
Both these solutions have the disadvantages of adding components and circuits and consequently of congesting the useful surface area of the memory. To increase the performance of an integrated circuit, designers always seek to make maximum profit from the useful surface area, and they are reluctant to give up part of the surface area to make up for possible later defects in the memory. This
REFERENCES:
patent: 3958228 (1976-05-01), Coombes et al.
patent: 4168541 (1979-09-01), DeKarske
patent: 4234935 (1980-11-01), Schreiner
patent: 4562536 (1985-12-01), Keeley et al.
patent: 4706136 (1987-11-01), Wentzel et al.
patent: 4744049 (1988-05-01), Kuban et al.
patent: 4809276 (1989-02-01), Lemay et al.
patent: 5031054 (1991-07-01), Lewis
patent: 5070502 (1991-12-01), Supnik
patent: 5075804 (1991-12-01), Beyring
patent: 5200959 (1993-04-01), Gross et al.
patent: 5216655 (1993-06-01), Hearn et al.
patent: 5299160 (1994-03-01), Mori
patent: 5299318 (1994-03-01), Bernard et al.
Bernard Christian
Charlot Didier
Keryvel Josiane
Beausoliel, Jr. Robert W.
Bull S.A.
De'cady Albert
Kondracki Edward J.
LandOfFree
Integrated memory, method for managing it, and resultant informa does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated memory, method for managing it, and resultant informa, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated memory, method for managing it, and resultant informa will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1792997