Processor

Details Processor Processor

1994-09-30

1996-07-16

Lall, Parshotam S.

Boots, shoes, and leggings

364DIG1, 364DIG2, G06F 938

Patent

active

055375618

ABSTRACT:
A processor with a plurality of operational pipelines for performing parallel processing which is includes an instruction processing section with a plurality of instruction processing pipelines and an instruction processing control section with a plurality of instruction processing control pipelines. The instruction processing control section has an instruction issuing control section which issues decoded instructions after adding tags representing data dependency between successive instructions and a pipe lock signal generating section which generates pipe lock signals for locking the pipelines until further processing is allowed.

REFERENCES:
patent: 4750112 (1988-06-01), Jones et al.
patent: 4760519 (1988-07-01), Papworth et al.
patent: 4777594 (1988-10-01), Jones et al.
patent: 4789925 (1988-12-01), Lahti
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4969117 (1990-11-01), Mirankev
patent: 5155816 (1992-10-01), Kohn
Instruction Issue Logic for High-Performance Intempliple, Multiple Functional Unit Pipelined Computers, by Sohi IEEE Mar. 1990, pp. 349-359.
Intel's 80960, by Ryan, IEEE Jun. 1988 Publication, pp. 63-76.
The 1960CA Supersealar Implementation Of The 80960 Architecture, by McGeady, 1990 IEEE Publication, pp. 232-240.
Parallel Multi-Contex Architecture with High-Speed Synchronization Mechanism by Shimada et al IEEE Feb. 1991, Publication.

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