Method of and apparatus for bus control and data processor

Details Method of and apparatus for bus control and data processor Method of and apparatus for bus control and data processor

1993-11-10

1996-07-16

Harvey, Jack B.

395452, H01J 1300

Patent

active

055375537

ABSTRACT:
In a processor having a central processing unit, an instruction cache and a data cache, a bus controller is provided for controlling giving and receiving of a signal between internal instruction and data buses and external bus. Upon concurrent miss of instruction cache and data cache, the bus controller executes an external instruction access with priority in case where the external instruction access is a same page access as a previous external DRAM access, and executes an external data access in the other cases. Thereby, the cycle number required for the external access is reduced, while reducing the number of instruction execution cycles as a total.

REFERENCES:
patent: 4933835 (1990-06-01), Sachs et al.
patent: 4933837 (1990-06-01), Freidin
patent: 5179687 (1993-01-01), Hidaka et al.
patent: 5303364 (1994-04-01), Mayer et al.
patent: 5335336 (1994-08-01), Kametahi
patent: 5347643 (1994-09-01), Kondo et al.
patent: 5353415 (1994-10-01), Wolford et al.

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