Excavating
Patent
1994-08-15
1996-10-29
Beausoliel, Jr., Robert W.
Excavating
364266, 364DIG1, G06F 1100
Patent
active
055703836
ABSTRACT:
Apparatus and method for detecting timing hazards which might be introduced in a pattern for execution on a tester when edges are improperly programmed in the pattern. The apparatus includes hazard detection circuits associated with the pins of the tester. Each circuit receives control inputs which specify which edges are involved in the hazard and limits on the permissible time between the specified edges. In operation, the pattern is executed repeatedly, once for each hazard which must be detected. The programmed times for the selected edge as well as the drive and format for each period of the pattern are variable inputs to the circuit.
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Soboleski, "Using High Level Design Models for Generation of Test Vectors" IEEE pp. 345-348.
Gasbarro et al "Integrated Pin Electronics for VLSI Functional Testers" IEEE 1989 pp. 331-337.
Low et al. "An Integrated Functional Tester for CMOS Logic" 1993 IEEE pp. 453-456.
Brown Benjamin J.
Reichert Peter A.
Beausoliel, Jr. Robert W.
De'cady Albert
Teradyne, Inc.
Walsh Edmund J.
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