Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-04-22

1998-02-17

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800

Patent

active

057198209

ABSTRACT:
Variation of an address signal is detected by an address transition detecting circuit. The trailing edge of a detection pulse ATD is delayed by a delay control circuit to generate a control signal .PHI. with an expanded pulse width. Selection of word lines of a memory array is controlled depending upon a row address signal by a row decoder. The selected word line is activated only during the pulse period of the control signal .PHI.. Before making the output of the row decoder into non-active state, the output of a sense amplifier is latched by a latch circuit by the control signal .PHI. to output to an output circuit. Thus, double selection of the memory cell in transition of the drive signal of the word lines to be selected will never occur, thus avoiding the necessity of measuring for double selection, and the memory access period is shortened.

REFERENCES:
patent: 5515323 (1996-05-01), Yamazaki et al.

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