Non-volatile semiconductor memory device incorporating data latc

Details Non-volatile semiconductor memory device incorporating data latc Non-volatile semiconductor memory device incorporating data latc

1991-01-28

1994-11-08

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

36518905, 3652385, 365900, G11C 1602

Patent

active

053633300

ABSTRACT:
A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

REFERENCES:
patent: 4805151 (1989-02-01), Terada et al.
patent: 4891791 (1990-01-01), Iijima
patent: 4953129 (1990-08-01), Kobayashi et al.
patent: 5134583 (1992-07-01), Matsuo et al.
patent: 5136546 (1992-08-01), Fukuda et al.

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