Boots – shoes – and leggings
Patent
1985-12-18
1990-02-27
Shaw, Gareth D.
Boots, shoes, and leggings
3649272, 3649659, 3649500, 3649483, 3649650, 36518901, 36518904, G11C 700
Patent
active
049051890
ABSTRACT:
First binary bits are read synchronously relative to clock signals (e.g. 125 MH.sub.z) from first memory positions and second binary bits are read from, or written in, second memory positions asynchronously relative to the clock signals without affecting the reading of the first memory bits. For synchronously reading the first bits, a plurality of channels are sequentially activated at a suitable frequency (e.g. 25 megahertz). Information from pairs of data lines are introduced into a pair of buses at the clock frequency. The information in the buses is sampled upon the occurrence of the first polarity in synchronizing signals having frequency (e.g. 62.5 MH.sub.3) derived from the clock signals and is prolonged and evaluated in a first pair of output lines upon the occurrence of the second polarity in the synchronizing signals. The information being evaluated is introduced to such output lines during the occurrence of the first polarity in the synchronizing signals. The evaluated signals on such output lines are then neutralized upon the occurrence of the first polarity in such synchronizing signals. Similarly, the information in the buses is sampled upon the occurrence of the second polarity in the synchronizing signals and is prolonged and evaluated in a second pair of output lines upon the occurrence of the first polarity in the synchronizing signals. The evaluated signals on all of the output lines are then processed on an exclusive basis to insure that only one of the evaluated signals can be introduced at any one time to a resultant line.
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Brooktree Corporation
Napiorkowski Maria
Roston Ellsworth R.
Schwartz Charles H.
Shaw Gareth D.
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