PLL oscillator package and production method thereof

Details PLL oscillator package and production method thereof PLL oscillator package and production method thereof

1997-10-07

2000-06-27

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 25, 331 34, 331 36C, 331 68, 331158, 331177R, H01L 2350, H01L 2516, H03L 718

Patent

active

060811641

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a PLL oscillator and a piezoelectric oscillator, composed of a semiconductor integrated circuit and a piezoelectric resonator, for supplying a clock signal to a microcomputer or the like.


BACKGROUND TECHNOLOGY

Referring to FIG. 20, a first example of a conventional oscillator consisting of a semiconductor integrated circuit and a piezoelectric resonator for generating a clock signal to a computer or the like will be described below. A plurality of quartz oscillators 203 each including a piezoelectric resonator such as a quartz resonator 202 are mounted on a circuit board 201 of a computer system. Clock signals with various frequencies are generated by the respective quartz oscillators 203 and supplied to various units such as a CPU unit 204, an HDD unit 205, and communication units 206. Thus, the computer system needs as many quartz oscillators 203 as the number of clock frequencies. Furthermore, some units such as the CPU and HDD need a clock signal at a high frequency equal to or higher than 40 MHz. For such purpose, in the conventional technique, a clock signal is generated using a quartz oscillator operated in an overtone oscillation mode. FIG. 21 illustrates an example of a basic circuit of an overtone oscillator.
FIG. 22 illustrates a second example of a conventional PLL oscillator using a PLL circuit. This PLL oscillator includes an oscillation circuit coupled to a 14.31818-MHz quartz resonator for generating an oscillation signal and a PLL circuit which operates using the above oscillation signal as a reference signal. The frequency of the output signal is determined by the oscillation frequency of the quartz resonator and the frequency dividing ratio of a programmable frequency divider in the PLL circuit. The frequency dividing ratio of the programmable PLL frequency divider can be selected from two or more values so as to set the output frequency to a desired value.
Conventionally, a clock generator is realized using a quartz oscillator formed by combining a quartz resonator and an IC chip such as a CMOS IC chip. To generate a clock signal at a particularly high frequency supplied to a CPU, HDD, or the like, a quartz oscillator is operated in an overtone oscillation mode. However, the overtone oscillator circuit is difficult to operate in a stable fashion. More specifically, in the case of a 3rd-order overtone oscillator circuit, it is required that the circuit can selectively capture only a 3rd-order overtone signal while other signals at 1st- and 5th-order overtone frequencies should be suppressed. FIG. 23 illustrates a typical example of the negative resistance versus frequency characteristic of the overtone oscillator circuit. In FIG. 23, the curve 210 represents the characteristic of an oscillating circuit designed to operate at 50 MHz in the 3rd-order overtone mode. The negative resistance becomes maximum at 50 MHz corresponding to the 3rd-order overtone frequency, while the circuit has smaller negative resistances at 16.6 MHz corresponding to the 1st-order frequency and at 83.3 MHz corresponding to the 5th-order overtone frequency. As a result, oscillation occurs at 50 MHz corresponding to the 3rd-order overtone frequency. The negative resistance versus frequency characteristic varies depending on the gate capacitance (Cg), drain capacitance (Cd), feedback resistance (Rf), and the amplification factor (a) of an inverter. Therefore, if these parameters vary, the 3rd-order overtone oscillation can become unstable. As a result, even a jump to another order overtone mode can occur. More specifically, if the gate capacitance, drain capacitance, or feedback resistance increases, or the amplification factor of the inverter decreases, the negative resistance versus frequency characteristic shifts to left along the frequency axis This can cause a jump in oscillation to the fundamental frequency mode. On the other hand, if the gate capacitance, drain capacitance, or feedback resistance decreases, or the amplification factor of the inverter

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patent: 5703540 (1997-12-01), Gazda et al.
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