Method of manufacturing a bipolar transistor operating at low te

Details Method of manufacturing a bipolar transistor operating at low te Method of manufacturing a bipolar transistor operating at low te

1994-10-12

1996-10-29

Fourson, George

Fishing, trapping, and vermin destroying

437 28, 437162, 148DIG10, 148DIG11, 148DIG124, 148DIG35, 148DIG36, H01L 21265

Patent

active

055696112

ABSTRACT:
In a method of manufacturing a bipolar transistor, an oxide film pattern is formed on an epitaxial collector layer of a first conductive type which is formed on a buried layer of the first conductive type. A selectively-ion-implanted-collector (SIC) region is then formed in the collector layer, and after that, a base layer is grown on the SIC region with an inversely graded impurity distribution profile.

REFERENCES:
patent: 4729965 (1988-03-01), Tamaki et al.
patent: 5106767 (1992-04-01), Comfort et al.
patent: 5217909 (1993-06-01), Bertagnolli
patent: 5279976 (1994-01-01), Hayden et al.
patent: 5296391 (1994-03-01), Sato et al.
patent: 5302535 (1994-04-01), Imai et al.
patent: 5321301 (1994-06-01), Sato et al.
patent: 5323057 (1994-06-01), Cook et al.
patent: 5424228 (1995-06-01), Imai
patent: 5432104 (1995-07-01), Sato
J. F. Ziegler "Experimental Evaluation of . . . Transistor Pedestal Collector", IBM J. Res. Develop., Nov. 1971, pp. 452-456.
"Base-Emitter Injection Characterization in Low-Temperature Pseudo-Heterojunction Bipolar Transistors", IEEE Transactions on Electron Devices, vol. 37, No. 10, Oct. 1990, by Kazuo Yano et al., pp. 2222-2229.
"Reduction of f.sub.t by Nonuniform Base Bandgap Narrowing", IEEE Electron Device Letters, vol. 10, No. 8, Aug. 1989, by Simon Szeto et al., pp. 341-343.
"Profile Scaling Constraints for Ion-Implated and Epitaxial Bipolar Technology Designed for 77K Operation", 1991, IEEE, by John D. Cressler et al., pp. 861-864.
"Low Temperature Operation of Si and SiGe Bipolar Transistors", 1990 IEEE, by E. F. Crabbe et al., pp. 17-20.
"Measurment of Electron Lifetime, Electron Mobility and Band-Gap Narrowing in Heavily Doped p-Type Silicon", 1986 IEEE, by S. E. Swirhun et al., pp. 24-27.
"Measurment of Steady-State Minority-Carrier Transport Parameters in Heavily Doped n-Type Silicon", 1987 IEEE, by Jesus A. Del Alamo et al., pp. 1580-1589.
"Base Profile Design for High-Performance Operation of Bipolar Transistors at Liquid-Nitrogen Temperature", 1989 IEEE, by Johannes M. C. Stork et al., pp. 1503-1509.
"Ultra High Speed Bipolar Device", by T. Sugano, published by Baihuukan, pp. 36-39.

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