Method of manufacturing a wiring arrangement for a semiconductor

Details Method of manufacturing a wiring arrangement for a semiconductor Method of manufacturing a wiring arrangement for a semiconductor

1994-11-29

1996-07-16

Fourson, George

Fishing, trapping, and vermin destroying

437 53, 437193, 437195, 437203, H01L 2128

Patent

active

055366783

ABSTRACT:
An integrated circuit has an interconnection pattern which is recessed in the insulating layer, for example, an oxide layer. A groove is etched in the insulating layer corresponding to the metal pattern by means of a mask which is the inverted image of the interconnection pattern during manufacture. Etching is continued until contact windows are fully opened. To prevent the oxide between the contact windows also being removed, a conductive etching stopper layer is provided in the oxide layer. A layer already present in the process is used for this etching stopper layer, for example, a polycrystalline silicon layer, so that extra process steps are made redundant.

REFERENCES:
patent: 4163239 (1979-07-01), Carter
patent: 4789648 (1988-12-01), Chow et al.
patent: 4808552 (1989-02-01), Anderson
patent: 5396092 (1995-03-01), Peek

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