Fishing – trapping – and vermin destroying
Patent
1996-09-06
1998-02-17
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 44, 437 67, 437203, H01L 21266
Patent
active
057190674
ABSTRACT:
A field effect transistor and method for making same in which a first source/drain impurity distribution is located at a first depth below an upper surface of the semiconductor substrate and a second source/drain impurity distribution is located at a second depth below the upper surface. In a presently preferred embodiment, the first depth is greater than the second depth such that the transistor includes a channel region having a vertical component. The channel region extends from the first source/drain impurity distribution to the second source/drain impurity distribution. The field effect transistor further includes a gate dielectric which is in contact with the channel region and a conductive gate structure in contact with the gate dielectric layer. The vertical component of the transistor channel length can be accurately controlled with plasma etch techniques. In this manner, the transistor channel length is not defined by a photolithography process and, therefore, dimensions smaller than the minimum feature size resolvable by a photolithography aligner can be achieved.
REFERENCES:
patent: 4683643 (1987-08-01), Nakajima et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5180680 (1993-01-01), Yang
patent: 5250450 (1993-10-01), Lee et al.
Gardner Mark I.
Hause Fred N.
Advanced Micro Devices , Inc.
Chaudhari Chandra
Lally Joseph P.
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