Method of producing a mesa embedded type optical semiconductor d

Details Method of producing a mesa embedded type optical semiconductor d Method of producing a mesa embedded type optical semiconductor d

1991-08-02

1994-11-08

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437126, 437133, 437228, H01L 2120

Patent

active

053626745

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to an optical semiconductor device and method of producing the same and more specifically to a structure of an optical semiconductor device and a method of producing the same such as semiconductor laser providing a mesa structure, optical modulator, optical filter or photosensitive element.
A mesa embedded type optical semiconductor device is typically known as an example of the structure of optical semiconductor device.
This structure is formed by etching a multilayer structure of various semiconductor layers principally working as optical semiconductor device into the mesa type structure and then embedding both sides of such structure within a semiconductor layer for rejecting current.
The mesa embedded type optical semiconductor device must be produced in the stabilized high quality because it plays a very important role as the device for realizing an optical communication system or optical computer system.


PRIOR ART

FIG. 1 and FIG. 2 are diagrams indicating the mesa structure of the prior art through the sectional views of principal producing processes of a mesa embedded type InP system semiconductor laser.
In these figures, the reference numeral 1 denotes InP substrate; 2, active layer consisting of InGaAsP or InGaAs; 3, InP clad layer; 4, InGaAsP contact layer; 5, etching mask consisting of silicon dioxide.
The mesa type structure 10 is formed by etching a part of the contact layer 4, clad layer 3, active layer 2 and substrate 1 using the etchant consisting of brommethanol.
Moreover, the mesa type structure 10 shown in FIG. 2 is formed by etching a semiconductor layer formed by the InP material with chloric acid or hydrogen bromide and also etching a semiconductor layer formed by InGaAsP or InGaAs material with an etchant consisting of sulfuric acid system.
In FIG. 1 and FIG. 2, the flat area of substrate has the (100) plane.
In the structure shown in FIG. 1 and FIG. 2, both sides of mesa type structure 10 are embedded within the InP system semiconductor layer (current rejection layer) which defines a current path.
However, in the case of prior art shown in FIG. 1 and FIG. 2, a semiconductor layer is grown by the metalorganic chemical vapor deposition (MOCVD) method for embedding both sides of mesa structure and this growth layer is sometimes exposed out from the (111) B plane during the growing process.
The (111) B plane grows very slowly in the MOCVD method in comparison with that of the (100) plane forming the flat surface of the substrate and therefore when this plane is exposed, a problem that irregular growth areas or holes are generated in the grown semiconductor layer is generated.
FIG. 3 shows an example where both sides of mesa type structure 10 shown in FIG. 1 are embedded in the semiconductor layer 6. FIG. 4 also shows an example where both sides of mesa type structure 10 are embedded in the semiconductor layer 6 consisting of high resistance InP.
In the example where the structure of FIG. 1 is embedded in the semiconductor layer 6, irregular growth area 6A is generated as shown in FIG. 3.
Moreover, in the example where the structure of FIG. 2 is embedded in the semiconductor layer 6, holes 6B are generated as shown in FIG. 4.
The structures shown in FIG. 3 and FIG. 4 show the examples where normal growth is disabled due to exposition of the (111) B plane in the course of the growth.
After completion of embedded growth, golde, for example, is deposted as the electrode material.
However, gold easily diffuses into semiconductor material and it is necessary to deposit the TiPt layer as a barrier layer, etc. prior to the deposition of gold. Therefore, since it is difficult to deposit the barrier layer on the abnormally grown complicated region in FIG. 3 or in the hole region in FIG. 4, gold is deposited in direct in such regions.
The region where gold is deposited in direct allows formation of a conductive path by diffusion of gold and accordingly a leak current is easily generated and good performance cannot be obtained.


OBJECT AND D

REFERENCES:
patent: 4662998 (1987-05-01), Renner
patent: 4797374 (1989-01-01), Scott et al.
Electronics Letters, vol. 24, No. 24, 24 Nov. 1988, Stevenage, Herts, GB pp. 1483-1484.
Journal of Applied Physics, vol. 64, No. 7, 1 Oct. 1988, New York, US pp. 3684-3689.

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