Fishing – trapping – and vermin destroying
Patent
1993-06-24
1994-11-08
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 62, 437228, 148DIG50, H01L 2176
Patent
active
053626699
ABSTRACT:
A method is provided for forming a fully planarized trench isolated region in a semiconductor substrate for an integrated circuit, for example, a trench isolated field oxide region, or a trench isolated semiconductor region in which thin film semiconductor devices are formed. Planarization is accomplished by a chemical mechanical polishing process in which coplanar layers of a chemical mechanical polish resistant material are provided in a centre region of wide trenches as well as on the semiconductor substrate surface adjacent the trenches. The chemical mechanical polish resistant layer in the centre region of a wide trench forms an etch stop to prevent dishing of layers filling the trench during overall wafer planarization by chemical mechanical polishing. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuit structures.
REFERENCES:
patent: 4255207 (1981-03-01), Nicolay et al.
patent: 4396460 (1983-08-01), Tamaki et al.
patent: 4570330 (1986-02-01), Cogan
patent: 4671851 (1987-06-01), Beyer et al.
patent: 4740480 (1988-04-01), Ooka
patent: 4836885 (1989-06-01), Breiten et al.
"Method for producing planarized polysilicon filled trenches" 2244 Research Disclosure (1989) Oct., No. 306.
Boyd John M.
Ellul Joseph P.
Tay Sing P.
Dang Trung
de Wilton Angela C.
Hearn Brian E.
Northern Telecom Limited
LandOfFree
Method of making integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making integrated circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1782197