Method of producing a self-aligned contact penetrating cell plat

Details Method of producing a self-aligned contact penetrating cell plat Method of producing a self-aligned contact penetrating cell plat

1994-03-15

1994-11-08

Thomas, Tom

Fishing, trapping, and vermin destroying

437 44, 437 47, 437 60, 437919, H01L 2170

Patent

active

053626664

ABSTRACT:
After formation of the storage poly in a stacked capacitor DRAM, the oxide 1 layer is partially etched to leave a thick oxide deposition in the area of the future bit line contact, upon which the cell poly is deposited, followed by oxide 2 and then a poly or nitride layer. A mask and etch process forms the bit line contact region through the cell poly, then a thin oxide is deposited and etched along with the oxide 1 to form cell poly spacers that don't close off the active area. The poly or nitride on top of the oxide 2 forms a hard mask that allows the spacers to travel down the side walls of the contact region creating a contact region that is wider at the top than bottom, facilitating metalization.

REFERENCES:
patent: 4543707 (1985-10-01), Ito et al.
patent: 5061651 (1991-10-01), Ino
patent: 5077238 (1991-12-01), Fujii et al.
patent: 5135881 (1994-08-01), Saelci
patent: 5150276 (1992-09-01), Gonzales
Kawamoto et al., "A 1.28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64Mb DRAMS", Symposium on VLSI Technology, 1990, pp. 13-14.
Itoh et al., "Two Step Deposited Rugged Surface (TDRS) Storagenode and Self Aligned Bitline-Contact Penetrating Cellplate (SABPEC) for 64 MbDRAM STC Cell" IEEE Symposium on VLSI Technology, 1991, pp. 9-10.
Shibata et al., "A Novel Zero-Overlap/Enclosure Metal Interconnection Technology for High Density Logic VLSI's", IEEE VMIC Conference, 1990, pp. 15-21.

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