Method and apparatus for translating virtual addresses in a data

Details Method and apparatus for translating virtual addresses in a data Method and apparatus for translating virtual addresses in a data

1993-11-02

1995-10-31

Kim, Ken S.

Boots, shoes, and leggings

364228, 3642557, 3642434, 364DIG1, 364964343, 364DIG2, 3649555, 395800, 39542103, 395416, G06F 1210

Patent

active

054637503

ABSTRACT:
A computing system has multiple instruction pipelines, wherein one or more pipelines require translating virtual addresses to real addresses. A TLB is provided for each pipeline requiring address translation services, and an adress translator is provided for each such pipeline for translating a virtual address recieved from its associated pipeline into corresponding real addresses. Each address translator comprises a translation buffer accessing circuit for accessing the TLB, a translation indicating circuit for indicating whether translation data for the virtual address is stored in the translation buffer, and an update control circuit for activating the direct address translation circuit when the translation data for the virtual address is not stored in the TLB. The update control circuit also stores the translation data retrieved from the main memory into the TLB. If it is desired to have the same translation information available for all the pipelines in a group, then the update control circuit also updates all the other TLB's in the group.

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