System for detecting non-coincidence of codes

Details System for detecting non-coincidence of codes System for detecting non-coincidence of codes

1993-06-21

1995-10-31

Baker, Stephen M.

Excavating

3401462, 3701051, 3701054, 375368, H04L 710

Patent

active

054636450

ABSTRACT:
An input coded signal is compared with a predetermined coded signal to generate a non-coincidence signal. Error bits of the non-coincidence signal are changed to correct bits by a predetermined number of bits. When the non-coincidence signal has no longer any error bits as a result of changing the error bits to the correct bits, the input coded signal is determined to be correct.

REFERENCES:
patent: 4447903 (1984-05-01), Sewerinson
patent: 4649543 (1987-03-01), Levine
patent: 5073932 (1991-12-01), Yossifor et al.
patent: 5218562 (1993-06-01), Basehore et al.
Patent Abstracts of Japan, vol. 5, No. 163, Oct. 1981.
P. L. O'Leary, "10-MHz 64-bit Error-Tolerant Signature Recognition Circuit", IEEE Journal of Solid-State Circuits, vol. 23, No. 3, Jun. 1988, pp. 625-629.
Electronics International, vol. 53, No. 23, Oct. 1980, New York, p. 260.

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